DELIVERY AND REQUIRED RESOURCES

The T-COR-31 IP core is supplied as archive file to be in-cluded into Xilinx® Vivado IDE projects or as a QSP file and VERILOG file with description of input/output ports for Altera® Quartus IDE system. Below is the list of resources required for FPGA Xilinx® 7 series ICs.

  • LUT ~ 39000 (Xilix 7 series);
  • FF (Registers) ~ 46000 (Xilix 7 series);
  • BRAM ~ 82 (Xilix 7 series) (Xilix 7 series);
  • DSP ~ 16 (Xilix 7 series);

FIELD OF APPLICATIONS

The IP core can be used in smart sights, portable and stationary target acquisition systems, unmanned aerial vehicles, weapon stations, fire control systems, anti-aircraft complexes and homing heads.

HOSTING PLATFORMS AND COMPATIBILITY

The FPGA IP core can make use of any computer modules based on microcircuits manufactured by Xilinx® and Altera® companies. Besides, the core can be adapted for use in application-specific integrated circuits (ASIC). Owing to easy integration, fast prototyping is possible for evaluation of the IP core performance characteristics. The device is compatible with Xilinx® Vivado and Altera® Quartus IDE systems.


DOWNLOADS

 T-COR-31 Brochure

T-COR-31 Brochure

 T-COR-31 Demo IP core for Xilinx 7 Series

T-COR-31 Demo IP core for Xilinx 7 Series

 T-COR-31 Programmer manual

T-COR-31 Programmer manual

 T-COR-31 Demo IP core for Xilinx SPARTAN 6 Series

T-COR-31 Demo IP core for Xilinx SPARTAN 6 Series

 

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